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State Machine
6
State Machine
Figure 3 details the state machine.
Power ON
AND ENABLE=0
State 1
Standby mode
ENABLE=0
ENABLE=1
State 2
PLL out of lock-in range
No RF output
ENABLE=0
State 4
Shutdown mode
PLL in
lock-in range
PLL out of
lock-in range
V battery < V shutdown
State 3
Transmission mode
Figure 3. State machine
State 1: The circuit is in standby mode and draws only a leakage current from the power supply.
State 2: In this state, the PLL is out of the lock-in range; therefore, the RF output stage is switched off, preventing RF
transmission. Data clock is available on the DATACLK pin. Each time the device is enabled, the state machine passes through
this state.
State 3: In this state, the PLL is within the lock-in range. If t < t PLL_lock_in , the PLL may be in acquisition mode. If t ≥ t PLL_lock_in ,
then the PLL is locked. Data entered on the DATA pin are output on the RFOUT pin according to the modulation selected by
the level applied on the MODE pin.
State 4: When the supply voltage falls below the shutdown voltage threshold (V SDWN ,) the entire circuit switches off. After this
shutdown, applying a low level on the ENABLE pin unlatches the circuit.
Figure 4 shows the waveforms of the main signals for a typical application cycle.
PLL Tuned UHF Transmitter for Data Transfer Applications, Rev. 1.7
6
Freescale Semiconductor
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